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Operating Environment Architecture (OEA)
Table 3-37. Register Settings Following an Instruction Protection Exception
Register Name
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
Execution resumes at offset 0x1300 from the base address indicated by MSR[IP].
3.15.4.15 Implementation-Specific Data Protection Error Exception
(0x1400)
The implementation-specific data protection error exception occurs in the following case:
• The data access violates the storage protection and MSR[DR]=1. See Chapter 11,
"L-Bus to U-Bus Interface (L2U)."
See Table 3-38 for data-protection-error exception register settings.
Table 3-38. Register Settings Following a Data Protection
Register Name
Save/Restore Register 0 (SRR0)
3-62
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Bits
1
All
Set to the effective address of the instruction that caused the
exception
0:2
Cleared to 0
3
Set to 1 if the fetch access was to a guarded storage when
MSR[IR] = 1, otherwise clear to 0
4
Set to 1 if the storage access is not permitted by the protection
mechanism (IMPU in BBC) and MSR[IR] = 1; otherwise clear to
0
5:15
Cleared to 0
16:31
Loaded from bits [16:31] of MSR. In the current implementation,
bit 30 of the SRR1 is never cleared, except by loading a zero
value from MSR[IR]
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
This bit is set according to (BBCMCR[EN_COMP] and
BBCMCR[EXC_COMP])
Other
Cleared to 0
Error Exception
Bits
1
All
Set to the effective address of the instruction that caused the
exception
MPC533 Reference Manual
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