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Table J-2. Instruction Timing Examples for Different Buses (continued)
Note: L = L-bus, U = U-bus, E = E-bus, C = CMF (Flash), IMB = internal memory bus, DC = DECRAM
Access
1
Instruction Fetch->
cmf
2 consecutive
accesses and
External Bus-> cmf
E
1
N is the number of read cycle clocks from external address valid until external data valid. In the case of zero wait states,
N = 2.
2
Core instruction fetch data bus is usually the U-bus
3
8 clocks are dedicated for external accesses, and internal accesses are denied.
4
Assuming the external master immediately retries
Note: Shaded areas = address phase ; Non-shaded areas = data phase
MOTOROLA
2
3
4
5
C,U
U
3
C
—
—
4
Retry
E
Appendix J. Memory Access Timing
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Number of Clocks
6
7
8
9
—
—
—
—
U
U
E
10
11
12
13
—
—
U
U
Total
2
11
8
J-3
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