Recommended Simplified Mnemonics; Calculating Effective Addresses - Motorola MPC533 Reference Manual

Table 3-19. Instruction Set Summary (continued)
Mnemonic
stwu
stwux
stwx
subf (subf. subfo subfo.)
subfc (subfc. subfco subfco.)
subfe (subfe. subfeo subfeo.)
subfic
subfme (subfme. subfmeo subfmeo.)
subfze (subfze. subfzeo subfzeo.)
sync
tw
twi
xor (xor.)
xori
xoris
Note: The dot (.) suffix on a mnemonic indicates that the CR register update is enabled. The o suffix on a mnemonic
indicates that the overflow bit in the XER is enabled.
3.10.2

Recommended Simplified Mnemonics

To simplify assembly language coding, a set of alternative mnemonics is provided for some
frequently used operations (such as no-op, load immediate, load address, move register, and
complement register).
For a complete list of simplified mnemonics, see the RCPU Reference Manual. Programs
written to be portable across the various assemblers for the MPC500 architecture should not
assume the existence of mnemonics not described in that manual.
3.10.3

Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when executing
a memory access or branch instruction or when fetching the next sequential instruction.
The MPC500 architecture supports two simple memory addressing modes:
• EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate
index)
• EA = (rA|0) + rB (register indirect with index)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Operand Syntax
rS,d(rA)
rS,rA,rB
rS,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,SIMM
rD,rA
rD,rA
—
TO,rA,rB
TO,rA,SIMM
rA,rS,rB
rA,rS,UIMM
rA,rS,UIMM
Chapter 3. Central Processing Unit
Name
Store Word with Update
Store Word with Update Indexed
Store Word Indexed
Subtract From
Subtract from Carrying
Subtract from Extended
Subtract from Immediate Carrying
Subtract from Minus One Extended
Subtract from Zero Extended
Synchronize
Trap Word
Trap Word Immediate
XOR
XOR Immediate
XOR Immediate Shifted
Instruction Set
3-37