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Memory Map and Register Definitions
6.2.2.1
System Configuration Registers
System configuration registers include the SIUMCR, the IMMR, and the EMCR registers.
6.2.2.1.1
SIU Module Configuration Register (SIUMCR)
The SIUMCR contains bits which configure various features in the SIU module. The
register contents are shown below.
MSB
1
0
Field EARB
HRESET ID(0)
16
17
HRESET
0
ID(17:18)
Addr
The reset value is a reset configuration word value, extracted from the internal data bus line. Refer to Section 7.5.2,
"Hard Reset Configuration Word (RCW)."
Figure 6-12. SIU Module Configuration Register (SIUMCR)
All SIUMCR fields which are controlled by the reset
configuration word should not be changed by software while
the corresponding functions are active.
Bits
Name
0
EARB
External arbitration
0 Internal arbitration is performed
1 External arbitration is assumed
1:3
EARP
External arbitration request priority. This field defines the priority of an external master's
arbitration request. This field is valid when EARB is cleared. Refer to Section 9.5.7.4, "nternal
Bus Arbiter," for details.
4:7
—
Reserved
8
DSHW
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and flash EEPROM). This field is locked by the DLK bit. Note that
instruction show cycles are programmed in the ICTRL and L-bus data show cycles are
programmed in the L2UMCR.
0 Disable show cycles for all internal data cycles
1 Show address and data of all internal data cycles
9:10
DBGC
Debug pins configuration. Refer to Table 6-8.
11
DBPC
Reserved.
6-26
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
5
6
EARP
—
000_0000_0
18
19
20
21
22 23
WARNING
Table 6-7. SIUMCR Bit Descriptions
MPC533 Reference Manual
7
8
9
10
DSHW
DBGC
ID(9:10)
24
25
26
0_0000_0000_0000
0x2F C000
Description
11
12
13
14
—
ATWC
GPC
ID(11)
ID(12)
000
27
28
29
30
MOTOROLA
15
DLK
LSB
31
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