Motorola MPC533 Reference Manual page 1026

IEEE 1149.1 Test Access Port
• The JTAG output port, TDO, is configured with a weak pull-up .
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data
registers. A boundary scan register links all device signal pins into a single shift register.
The test logic implemented utilizes static logic design. The implementation provides the
capability to:
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the for a given circuit-board test by effectively reducing the boundary scan
register to a single cell.
3. Sample the system pins during operation and transparently shift out the result in
the boundary scan register.
4. Disable the output drive to pins during circuit-board testing.
Certain precautions must be observed to ensure that the IEEE
1149.-like test logic does not interfere with nontest operation.
23.1.1 Overview
An overview of the
implementation includes a TAP controller, a 4-bit instruction register, and two test registers
(a one-bit bypass register and a boundary scan register). This implementation includes a
dedicated TAP consisting of the following signals:
• TCK — a test clock input to synchronize the test logic. (with an internal pull-down
resistor)
• TMS — a test mode select input (with an internal pullup resistor) that is sampled on
the rising edge of TCK to sequence the TAP controller's state machine.
• TDI — a test data input (with an internal pullup resistor) that is sampled on the rising
edge of TCK.
• TDO — a three-state test data output that is actively driven in the shift-IR and
shift-DR controller states. TDO changes on the falling edge of TCK. (This pin also
has a weak pull-up that is active when output drivers are disabled, except during a
HI-Z instruction).
• TRST — an asynchronous reset with an internal pull-up resistor that provides
initialization of the TAP controller and other logic required by the standard. This
input is multiplexed with the PORESET signal.
• JCOMP — JTAG Compliancy – This signal provides JTAG IEEE1149.1
compatibility and selects between normal operation (low) and JTAG test mode
(high).
23-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
scan chain implementation is shown in Figure 23-2. The
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