Motorola MPC533 Reference Manual page 734

MIOS14 Programmer's Model
• The read/write and control bus
• The request bus
• The counter bus set
17.3.3 Read/Write and Control Bus
The read/write and control bus (RWCB) allows read and write data transfers to and from
any I/O submodule through the MBISM. It includes signals for data and addresses as well
as control signals. The control signals allow 16-bit simple synchronous single master
accesses and supports fast or slow master accesses.
17.3.4 Request Bus
The request bus (RQB) provides interrupt request signals along with I/O submodule
identification and priority information to the MBISM.
Some submodules do not generate interrupts and are therefore
independent of the RQB.
17.3.5 Counter Bus Set
The 16-bit counter bus set (CBS) is a set of six 16-bit counter buses. The CBS makes it
possible to transfer information between submodules. Typically, counter submodules drive
the CBS, while action submodules process the data on these buses. Note, however, that
some submodules are self-contained and therefore independent of the counter bus set.
17.4 MIOS14 Programmer's Model
The address space of the MIOS14 consist of 4 Kbytes starting at the base address of the
module (0x306000). The overall address map organization is shown in Figure 17-2.
17.4.1 Bus Error Support
A bus error signal is generated when access to an unimplemented or reserved 16-bit register
is attempted, or when a priviledge violation occurs. A bus error is generated under any of
the following conditions:
• Attempted access to unimplemented 16-bit registers within the decoded register
block boundary.
• Attempted user access to supervisor registers
• Attempted access to test registers when not in test mode
• Attempted write to read-only registers
17-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
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