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MIOS14 Pulse Width Modulation Submodule (MPWMSM)
MSB
1
2
0
Field
Reset
Addr 0x30 6004, 0x30 600C, 0x30 6014, 0x30 601C, 0x30 6024, 0x30 602C, 0x30 6084, 0x30 608C, 0x30 6094,
Figure 17-27. MPWMSM Counter Register (MPWMCNTR)
Bits
Name
0:15
CNT
Counter. These bits reflect the actual value of the MPWMSM counter.
17.10.6.5 MPWMSM Status/Control Register (MPWMSCR)
The status and control register gathers read only bits reflecting the status of the MPWMSM
signal as well as read/write bits related to its control and configuration.
MSB
1
0
Field PIN
DDR FREN TRSP POL
SRESET
U
Addr 0x30 6004, 0x30 600C, 0x30 6014, 0x30 601C, 0x30 6024, 0x30 602C, 0x30 6084, 0x30 608C, 0x30 6094,
Figure 17-28. MPWMSM Counter Register (MPWMCNTR)
Bits
Name
0
PIN
Pin input status bit — The PIN bit reflects the state present on the MPWMSM signal. The software
can thus monitor the pin state.
The PIN bit is a read-only bit. Writing to the PIN bit has no effect.
1
DDR
Data direction register — The DDR bit indicates the direction for the signal when the PWM
function is not used (disable mode).
0 signal is in input.
1 signal is in output.
The DDR bit is cleared by reset.
Table 17-31 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data
direction register (DDR) bit.
2
FREN
Freeze enable bit — This active high read/write control bit enables the MPWMSM to recognize
the freeze signal on the MIOB.
0 MPWMSM not frozen even if the MIOB freeze line is active.
1 MPWMSM frozen if the MIOB freeze line is active.
The FREN is cleared by reset.
17-58
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
4
5
6
0x30 609C, 0x30 60A4, 0x30 60AC
Table 17-29. MPWMCNTR Bit Descriptions
2
3
4
5
EN
000_00
0x30 609C, 0x30 60A4, 0x30 60AC
Table 17-30. MPWMSCR Bit Descriptions
MPC533 Reference Manual
7
8
9
10
CNT
Undefined
Description
6
7
8
9
10
—
Undefined
Description
11
12
13
14
11
12
13
14
CP
MOTOROLA
LSB
15
LSB
15
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