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Overview
Internal Addresses [0:16], AT[0:2]
Base
Register
Base Register 3 (BR3)
Dual Mapping
Base Register (DMBR)
Figure 10-2. Memory Controller Block Diagram
Most memory controller features are common to all four banks. (For features unique to the
CS[0] bank, refer to Section 10.7, "Global (Boot) Chip-Select Operation.") A full 32-bit
address decode for each memory bank is possible with 17 bits having address masking. The
full 32-bit decode is available, even if all 32 address bits are not MPC533 signals connected
to the external device.
Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to four
Gbytes. Each memory bank can be selected for read-only or read/write operation. The
access to a memory bank can be restricted to certain address type codes for system
protection. The address type comparison occurs with a mask option as well.
From 0 to 30 wait states can be programmed with TA generation. Four write-enable and
byte-enable signals (WE/BE[0:3]) are available for each byte that is written to memory. An
output enable (OE) signal is provided to eliminate external glue logic. A memory transfer
10-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Option
Register
0 (BR0)
1 (BR1)
2 (BR2)
Region Match Logic
Wait State
Counter
MPC533 Reference Manual
0 (OR0)
1 (OR1)
2 (OR2)
Option Register 3 (OR3)
Dual Mapping
Option Register (DMOR)
Attributes
General-Purpose
Expired
Chip-Select
Load
CS[0:3]
WE/BE[0:3]
Machine
OE
(GPCM)
MOTOROLA
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