Motorola MPC533 Reference Manual page 357

:
STS TS AT[0] AT[1] AT[2] AT[3]
1 x x x
1
0 0 0 0
1
1 ?
1 0 0
1
1 ?
1
Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
9.5.8.7 Burst Data in Progress
This signal is sent from the master to the slave to indicate that there is a data beat following
the current data beat. The master uses this signal to give the slave advance warning of the
remaining data in the burst. BDIP can also be used to terminate the burst cycle early. Refer
to Section 9.5.4, "Burst Transfer" and Section 9.5.5, "Burst Mechanism" for more
information. Refer to Section 10.9.3, "Memory Controller Base Registers (BR0–BR3)" for
memory controller BDIP options.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-8. Address Types Definition
PTR RSV
x x 1 1
0 0 0 1
1 1 1
1 0 1 0
1 1 1
0 0 0 1
1 1 1
1 0 1 0
1 1 1
? ? 1 1
0 0 0 1
1 1 1
1 0 1 0
1 1 1
0 0 0 1
1 1 1
1 0 1 0
1 1 1
? ? 1 1
Chapter 9. External Bus Interface
Address Space Definitions
No transfer
RCPU, normal instruction, program trace, supervisor mode
RCPU, normal instruction, supervisor mode
RCPU, reservation data, supervisor mode
RCPU, normal data, supervisor mode
RCPU, normal instruction, program trace, user mode
RCPU, normal instruction, user mode
RCPU, reservation data, user mode
RCPU, normal data, user mode
Reserved
RCPU, show cycle address instruction, program trace,
supervisor mode
RCPU, show cycle address instruction, supervisor mode
RCPU, reservation show cycle data, supervisor mode
RCPU, show cycle data, supervisor mode
RCPU, show cycle address instruction, program trace, user
mode
RCPU, show cycle address instruction, user mode
RCPU, reservation show cycle data, user mode
RCPU, show cycle data, user mode
Reserved
Bus Operations
9-41