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7.3
Data Coherency During Reset
The MPC533 supports data coherency and avoids data corruption during reset. If a cycle is
executing when any SRESET or HRESET source is detected, then the cycle will either
complete or will not start before generating the corresponding reset control signal. There
are reset sources, however, when the MPC533 generates an internal reset due to special
internal situations where this protection is not supported. See Section 7.4, "Reset Status
Register (RSR)."
In the case of large operand size (32 or 16 bits) transactions to a smaller port size, the cycle
is split into two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data
will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken down into
multiple cycles, data coherency is NOT assured between these cycles (i.e., data could be
corrupted).
Contention may occur if a write access is in progress to external memory and
SRESET/HRESET is asserted and the external reset configuration word (RCW) is used. In
this case, the external RCW drivers, usually activated by HRESET/SRESET lines, will
drive the RCW together with the MPC533. Thus the data in the RAM may be corrupted
regardless of data coherency mechanism in the MPC533.
Table 7-2. Reset Configuration Word and Data Corruption/Coherency
Reset Driven
HRESET
SRESET
HRESET & SRESET
7.4
Reset Status Register (RSR)
All of the reset sources are fed into the reset controller. The 16-bit reset status register
(RSR) reflects the most recent source, or sources, of reset. (Simultaneous reset requests can
cause more than one bit to be set at the same time.) This register contains one bit for each
reset source. A bit set to logic one indicates the type of reset that occurred.
Once set, individual bits in the RSR remain set until software clears them. Bits in the RSR
can be cleared by writing a one to the bit. A write of zero has no effect on the bit. The
register can be read at all times. The reset status register receives its default reset values
during power-on reset. The RSR is powered by the KAPWR pin.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Reset to Use for Data
Coherency (EXT_RESET)
SRESET
HRESET
HRESET || SRESET
Chapter 7. Reset
Data Coherency During Reset
Comments
Provided only one of them is driven into the
MPC533 at a time
7-5
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