Table of Contents
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Section
Audience ............................................................................................................ lxvii
Organization....................................................................................................... lxvii
Suggested Reading............................................................................................... lxx
Conventions and Nomenclature.......................................................................... lxxi
Notational Conventions .................................................................................... lxxiii
Acronyms and Abbreviations ........................................................................... lxxiii
References.......................................................................................................... lxxv
1.1
Introduction.......................................................................................................... 1-1
1.2
Block Diagram ..................................................................................................... 1-2
1.3
Key Features ........................................................................................................ 1-3
1.3.1
High Performance CPU System ...................................................................... 1-3
1.3.1.1
RISC MCU Central Processing Unit (RCPU) ............................................. 1-3
1.3.1.2
MPC5xx System Interface (USIU).............................................................. 1-4
1.3.1.3
Burst Buffer Controller (BBC) Module....................................................... 1-4
1.3.1.4
Flexible Memory Protection Unit................................................................ 1-5
1.3.1.5
Memory Controller ...................................................................................... 1-5
1.3.1.6
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) ............................ 1-5
1.3.1.7
32-Kbyte Static RAM (CALRAM) ............................................................. 1-5
1.3.1.8
General Purpose I/O Support (GPIO).......................................................... 1-6
1.3.2
Nexus Debug Port (Class 3)............................................................................. 1-6
1.3.3
Integrated I/O System ...................................................................................... 1-6
1.3.3.1
22-Channel Modular I/O System (MIOS14) ............................................... 1-6
1.3.3.2
1.3.3.3
One CAN 2.0B Controller (TouCAN) Module ........................................... 1-7
1.3.3.4
Queued Serial Multi-Channel Module (QSMCM) ...................................... 1-7
1.3.3.5
Peripheral Pin Multiplexing (PPM) ............................................................. 1-8
1.4
MPC533 Optional Features ................................................................................. 1-8
1.5
Comparison of MPC533 and MPC555 ................................................................ 1-8
1.6
Additional MPC533 Differences ......................................................................... 1-9
1.7
SRAM Keep-Alive Power Behavior.................................................................. 1-10
MOTOROLA
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Contents
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Chapter 1
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