Motorola MPC533 Reference Manual page 654

Serial Communication Interface
15.7.1 SCI Registers
The SCI programming model includes the QSMCM global and pin control registers and the
DSCI registers.
The DSCI registers, listed in Table 15-23, consist of five control registers, three status
registers, and 34 data registers. All registers may be read or written at any time by the CPU.
Rewriting the same value to any DSCI register does not disrupt operation; however, writing
a different value into a DSCI register when the DSCI is running may disrupt operation. To
change register values, the receiver and transmitter should be disabled with the transmitter
allowed to finish first. The status flags in register SCxSR can be cleared at any time.
Address
0x30 5008
0x30 500A
0x30 500C
0x30 500E
(non-queue mode only
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
0x30 502A
0x30 502C —
0x30 504A
0x30 504C-6A
*Reads access the RDRx; writes access the TDRx.
15-48
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15-23. SCI Registers
Name
SCI1 Control Register 0
SCC1R0
See Table 15-24 for bit descriptions.
SCI1 Control Register 1
SCC1R1
See Table 15-25 for bit descriptions.
SCI1 Status Register
SC1SR
See Table 15-26 for bit descriptions.
SCI1 Data Register
Transmit Data Register (TDR1)*
SC1DR
Receive Data Register (RDR1)*
See Table 15-27 for bit descriptions.
SCC2R0 SCI2 Control Register 0
SCC2R1 SCI2 Control Register 1
SC2SR SCI2 Status Register
SCI2 Data Register
SC2DR Transmit Data Register (TDR2)*
Receive Data Register (RDR2)*
QSCI1 Control Register
Interrupts, wrap, queue size and enables
QSCI1CR
for receive and transmit, QTPNT.
See Table 15-32 for bit descriptions.
QSCI1 Status Register
OverRun error flag, queue status flags,
QSCI1SR
QRPNT, and QPEND.
See Table 15-33 for bit descriptions.
QSCI1 Transmit Queue QSCI1 Transmit Queue Data locations (on
Memory Area half-word boundary)
QSCI1 Receive Queue QSCI1 Receive Queue Data locations (on
Memory Area half-word boundary)
MPC533 Reference Manual
Usage
MOTOROLA