Condition Register Crn Field - Compare Instruction; Integer Exception Register (Xer) - Motorola MPC533 Reference Manual

Table 3-8. Bit Settings for CR1 Field of CR (continued)
CR1 Bit
2 Floating-point invalid exception (VX).This is a copy of the final state of FPSCR[VX] at the completion of the
instruction.
3 Floating-point overflow exception (OX).This is a copy of the final state of FPSCR[OX] at the completion of
the instruction.
3.7.4.3 Condition Register CRn Field — Compare Instruction
When a specified CR field is set by a compare instruction, the bits of the specified field are
interpreted as shown in Table 3-9. A condition register field can also be accessed by the
mfcr, mcrf, and mtcrf instructions.
Table 3-9. CRn Field Bit Settings for Compare Instructions
1
CRn Bit
0 Less than, floating-point less than (LT, FL).
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) < (frB).
1 Greater than, floating-point greater than (GT, FG).
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB).
2 Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
3 Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the
instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
1
Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
3.7.5

Integer Exception Register (XER)

The integer exception register (XER), SPR 1, is a user-level, 32-bit register.
MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
0
Field SO OV
Reset Undefined
Addr
The bit descriptions for XER, shown in Table 3-10, are based on the operation of an
instruction considered as a whole, not on intermediate results. For example, the result of the
subtract from carrying (subfcx) instruction is specified as the sum of three values. This
instruction sets bits in the XER based on the entire operation, not on an intermediate sum.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
CA
00_0000_0000_0000_0000_0
Figure 3-8. Integer Exception Register (XER)
Chapter 3. Central Processing Unit
User Instruction Set Architecture (UISA) Register Set
Description
Description
—
SPR 1
31
BYTES
Undefined
3-19