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Bits
Name
0:16
AM
Address mask. This field allows masking of any corresponding bits in the associated base
register. Masking the address bits independently allows external devices of different size address
ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the
corresponding address bit to be used in comparison with the address signals. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. This field can be read or written at anytime.
Following a system reset, the AM bits are cleared in OR0.
17:19
ATM
Address type mask. This field masks selected address type bits, allowing more than one address
space type to be assigned to a chip-select. Any set bit causes the corresponding address type
code bits to be used as part of the address comparison. Any cleared bit masks the corresponding
address type code bit. Clear the ATM bits to ignore address type codes as part of the address
comparison. Note that the address type field uses only AT[0:2] and does not need AT[3] to define
the memory type space.
Following a system reset, the ATM bits are cleared in OR0.
20
CSNT
Chip-select negation time. Following a system reset, the CSNT bit is reset in OR0.
0 CS/WE are negated normally.
1 CS/WE are negated a quarter of a clock earlier than normal
Following a system reset, the CSNT bit is cleared in OR0.
21:22
ACS
Address to chip-select setup. Following a system reset, the ACS bits are reset in OR0.
00 CS is asserted at the same time that the address lines are valid.
01 Reserved
10 CS is asserted a quarter of a clock after the address lines are valid.
11 CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are cleared in OR0.
23
EHTR
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a
read access from the current bank and any MPC533 write accesses or read accesses to a
different bank.
0 Memory controller generates normal timing
1 Memory controller generates extended hold timing
Following a system reset, the EHTR bits are cleared in OR0.
24:27
SCY
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining the
length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If an external TA response is selected for this memory bank (by setting the SETA bit), then the
SCY field is not used.
Following a system reset, the SCY bits are set to 0b1111 in OR0.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 10-11. OR0–OR3 Bit Descriptions
Chapter 10. Memory Controller
Description
Programming Model
10-37
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