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1
1
1 1 1
R
R
R
R
R
T
T
T
T
T
1
1
1
1
1
* *
*
* *
* Restart RT Clock
15.7.7.8 Receiver Functional Operation
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver
contains a receive serial shifter and a parallel receive data register (RDRx) located in the
SCI data register (SCxDR). The serial shifter cannot be directly accessed by the CPU. The
receiver is double-buffered, allowing data to be held in the RDRx while other data is shifted
in.
Receiver bit processor logic drives a state machine that determines the logic level for each
bit-time. This state machine controls when the bit processor logic is to sample the RXD pin
and also controls when data is to be passed to the receive serial shifter. A receive time clock
is used to control sampling and synchronization. Data is shifted into the receive serial
shifter according to the most recent synchronization of the receive time clock with the
incoming data stream. From this point on, data movement is synchronized with the MCU
IMB3 clock. Operation of the receiver state machine is detailed in the Queued Serial
Module Reference Manual (QSMRM/AD).
The number of bits shifted in by the receiver depends on the serial format. However, all
frames must end with at least one stop bit. When the stop bit is received, the frame is
considered to be complete, and the received data in the serial shifter is transferred to the
RDRx. The receiver data register flag (RDRF) is set when the data is transferred.
The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE flag
in SCxSR is set. A framing error is usually caused by mismatched baud rates between the
receiver and transmitter or by a significant burst of noise. Note that a framing error is not
always detected; the data in the expected stop bit-time may happen to be a logic one.
Noise errors, parity errors, and framing errors can be detected while a data stream is being
received. Although error conditions are detected as bits are received, the noise flag (NF),
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
1
1 1
0
0
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R
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T
T
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T
T
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* *
* *
Figure 15-30. Start Search Example
Chapter 15. Queued Serial Multi-Channel Module
Serial Communication Interface
Perceived Start Bit
Actual Start Bit
0 0
0
0 0
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R
R
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T
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1 2
LSB
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*
15-61
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