Motorola MPC533 Reference Manual page 646

Queued Serial Peripheral Interface
bit in PORTQS that corresponds to the chip-select pin determines the base state of the
chip-select signal. If the base state is zero, chip-select assertion must be active high (PCS
bit in command RAM must be set); if base state is one, assertion must be active low (PCS
bit in command RAM must be cleared). PORTQS bits are cleared during reset. If no new
data is written to PORTQS before pin assignment and configuration as an output, the base
state of chip-select signals is zero and chip-select pins are configured for active-high
operation.
15.6.5.7 Optional Enhanced Peripheral Chip Selects
The MPC533 have an optional on-chip decoder for the peripheral chip selects. It is enabled
if any of the PCS[4:7]EN bits are enabled in the PDMCR2 register (see Table 2-6). The
decode translates the normal PCS[0:3] chip selects into a 1 of 8 decode. The polarity of the
new PCS outputs can be selected by the state of the PCSV bit in the PDMCR2. See
Table 15-22.
PCS_IN[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
15-40
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15-22. PCS Enhanced Functionality
PCS_OUT[7:0] IF PCSV = 0
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
00000000
RESERVED
MPC533 Reference Manual
PCS_OUT[7:0] IF PCSV = 1
11111110
11111101
11111011
11110111
11101111
11011111
10111111
01111111
11111111
RESERVED
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