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Watchpoints and Breakpoints Support
machine to branch to the appropriate exception handler. The CPU supports internal
watchpoints, internal breakpoints, and external breakpoints.
Internal watchpoints are generated when a user programmable set of conditions are met.
Internal breakpoints can be programmed to be generated either as an immediate result of
the assertion of one of the internal watchpoints, or after an internal watchpoint is asserted
for a user programmable times. Programming a certain internal watchpoint to generate an
internal breakpoint can be done either in software, by setting the corresponding software
trap enable bit, or on the fly using the serial interface implemented in the development port
to set the corresponding development port trap enable bit.
External breakpoints can be generated by any of the peripherals of the system, including
those found on the MPC533 or externally, and also by an external development system.
Peripherals found on the external bus use the serial interface of the development port to
assert the external breakpoint.
In the CPU, as in other RISC processors, saving/restoring machine state on the stack during
exception handling, is done mostly in software. When the software is in the middle of
saving/restoring machine state, the MSRRI bit is cleared. Exceptions that occur and that are
handled by the CPU when the MSRRI bit is clear result in a non-restartable machine state.
For more information refer to Section 3.15.4, "Exceptions."
In general, breakpoints are recognized in the CPU is only when the MSRRI bit is set, which
guarantees machine restartability after a breakpoint. In this working mode breakpoints are
said to be masked. There are cases when it is desired to enable breakpoints even when the
MSRRI bit is clear, with the possible risk of causing a non-restartable machine state.
Therefore internal breakpoints have also a programmable non-masked mode, and an
external development system can also choose to assert a non-maskable external breakpoint.
Watchpoints are not masked and therefore always reported on the external pins, regardless
of the value of the MSRRI bit. The counters, although counting watchpoints, are part of the
internal breakpoints logic and therefore are not decremented when the CPU is operating in
the masked mode and the MSRRI bit is clear.
Figure 21-2 shows the watchpoint and breakpoint support of the CPU.
MOTOROLA
Chapter 21. Development Support
21-13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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