Table of Contents
Advertisement
CLKOUT
BR
BG
BB
ADDR[0:27]
ADDR[28:29]
ADDR[30:31]
RD/WR
TSIZ[0:1]
1
BURST
TS
1
BDIP
Data
TA
BI
1 BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a
sequence of normal cycles.
Figure 9-19. Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
0
1
00
Chapter 9. External Bus Interface
2
3
Bus Operations
9-27
Advertisement
Table of Contents
