Motorola MPC533 Reference Manual page 1089

I.3.2 PLL External Components
VDDSYN and VSSSYN are the PLL dedicated power supplies. These supplies must be
used only for the PLL and isolated from all other noisy signals in the board. VDDSYN
could be isolated with RC filter (see Figure B-2), or LC filter. The maximum noise allowed
on VDDSYN, and VSSSYN is 50 mV with typical cut-off frequency of 500 Hz.
Keyed
VDD 2.6 V
Note: A filter cut off frequency of 500Hz is recommended, however this will result in a
capacitor size of 33uF using a 10 Ohm resistor. This may be too expensive or large
for the system. In this case the filter shown with cut- off frequency of 160kHz will suffice.
Keyed
VDD 2.6 V
Note: A filter cut off frequency of 500Hz is recommended, however this will result in a
capacitor size of 15uF using a 8.2mH inductor. This may be too expensive or large
for the system. In this case the filter shown with cut- off frequency of 5.5kHz will suffice.
I.3.3 PLL Off-Chip Capacitor C
C is the PLL feedback capacitor. It must be located as close as possible to the XFC and
XFC
VDDSYN pads. The maximum noise allowed on XFC is 50 mV peak-to-peak with a typical
cut-off frequency of 500 Hz.
The XFC capacitor creates a low pass filter in the PLL loop. The filter output feeds the PLL
VCO. The capacitor is charged and discharged by short current pulses, generated by the
phase detector. So the capacitor leakage and absorption directly affect the AC component
in the VCO input voltage that creates PLL output clock jitter. Therefore, the dielectric
quality of C should be high.
XFC
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Board
10 Ω
100 nF
VSSSYN
Figure I-5. RC Filter Example
Board
8.2 mH
100 nF
VSSSYN
Figure I-6. LC Filter Example (Alternative)
Appendix I. Clock and Board Guidelines
Crystal Oscillator External Components
MPC53x Device
VDDSYN
MPC53x Device
VDDSYN
XFC
I-5