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Development Port
CLKOUT
0
SRESET
DSDI
CLKEN
DSDI negates following SRESET negation
to enable clocked mode.
Internal clock enable signal asserts 8 clocks after SRESET
negation if DSDI is negated. This enables clocked mode.
First Start bit detected after DSDI negation (self clocked mode)
Figure 21-11. Enabling Clock Mode Following Reset
21.4.6.5 Development Port Serial Communications — Trap Enable
Mode
When not in debug mode the development port starts communications by setting DSDO
(the MSB of the 35-bit development port shift register) low to indicate that all activity
related to the previous transmission are complete and that a new transmission may begin.
The start of a serial transmission from an external development tool to the development port
is signaled by a start bit. A mode bit in the transmission defines the transmission as either
a trap enable mode transmission or a debug mode transmission. If the mode bit is set the
transmission will only be 10 bits long and only seven data bits will be shifted into the shift
register. These seven bits will be latched into the TECR. A control bit determines whether
the data is latched into the trap enable and VSYNC bits of the TECR or into the breakpoints
bits of the TECR.
21.4.6.6 Serial Data into Development Port — Trap Enable Mode
The development port shift register is 35 bits wide but trap enable mode transmissions only
use the start/ready bit, a mode/status bit, a control/status bit, and the seven least significant
data bits. The encoding of data shifted into the development port shift register (through the
DSDI pin) is shown in Table 21-13 and Table 21-14 below:
21-40
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
2
3
4
5
6
MPC533 Reference Manual
7
8
9
10
11
12
13 14
15
MOTOROLA
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