Motorola MPC533 Reference Manual page 1070

Table H-10. QSMCM A and B (Queued Serial Multi-Channel Module) (continued)
Address Access
0x30 5002 T
0x30 5004 S
0x30 5006 S
0x30 500A S/U
0x30 500C S/U
0x30 500E S/U
0x30 5010 — —
0x30 5012
0x30 5014 S/U
0x30 5016 S/U
0x30 5018 S/U
0x30 501A S/U
0x30 501C S/U
0x30 501E S/U
0x30 501F S/U
0x30 5020 S/U
0x30 5022 S/U
0x30 5024 S/U
0x30 5026 S/U
1
0x30 5028 S/U
2
0x30 502A S/U
H-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
QTEST_A QSMCM Test Register
QDSCI_IL_A Dual SCI Interrupt Level.
See Table 15-8 for bit descriptions.
QSPI_IL_A Queued SPI Interrupt Level.
See Table 15-9 for bit descriptions.
SCC1R1_A SCI1Control Register 1.
See Table 15-28 for bit descriptions.
SC1SR_A SCI1 Status Register.
See Table 15-29 for bit descriptions.
SC1DR_A SCI1 Data Register.
See Table 15-30 for bit descriptions.
— Reserved
PORTQS_A QSMCM Port QS Data Register.
See Section 15.5.1, "Port QS Data Register
(PORTQS)," for bit descriptions.
PQSPAR/ QSMCM Port QS PIn Assignment Register/
DDRQST_A QSMCM Port QS Data Direction Register.
See Table 15-14 for bit descriptions.
SPCR0_A QSPI Control Register 0.
See Table 15-17 for bit descriptions.
SPCR1_A QSPI Control Register 1.
See Table 15-17 for bit descriptions.
SPCR2_A QSPI Control Register 2.
See Table 15-20 for bit descriptions.
SPCR3_A QSPI Control Register 3.
See Table 15-21 for bit descriptions.
SPSR_A QSPI Status Register 3.
See Table 15-22 for bit descriptions.
SCC2R0_A SCI2 Control Register 0.
See Table 15-27 for bit descriptions.
SCC2R1_A SCI2 Control Register 1.
See Table 15-28 for bit descriptions.
SC2SR_A SCI2 Status Register.
See Table 15-29 for bit descriptions.
SC2DR_A SCI2 Data Register.
See Table 15-30 for bit descriptions.
QSCI1CR_A QSCI1 Control Register.
See Table 15-35 for bit descriptions.
QSCI1SR_A QSCI1 Status Register.
See Table 15-36 for bit descriptions.
MPC533 Reference Manual
Register Size Reset
16 S
16 S
16 S
16 S
16 S
16 S
— —
16 S
16 S
16 S
16 S
16 S
8 S
8 S
16 S
16 S
16 S
16 S
16 S
16 S
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