Motorola MPC533 Reference Manual page 610

Memory Maps
• Two idle-line detect modes
• Receiver active flag
QSMCM-enhanced SCI features:
• 16 register receive buffer on one SCI
• 16 register transmit buffer on one SCI
15.2.1 MPC533 QSMCM Details
The QSMCM module has an identical function to the MPC555. The MUXing of the pins is
controlled by the QPAPCS3 bit in the QSMCM pin assignment register (PQSPAR).
15.3 Memory Maps
The QSMCM memory maps, shown in Table 15-1 and Table 15-2, includes the global
registers, the QSPI and dual SCI control and status registers, and the QSPI RAM. The
QSMCM memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module. Refer
to Figure 4-3 for a diagram of the MPC533 internal memory map.
1
Access Address
S 0x30 5000
T 0x30 5002
S 0x30 5004
S 0x30 5006
S/U 0x30 5008
S/U 0x30 500A
S/U 0x30 500C
S/U 0x30 500E
S/U 0x30 5010
S/U 0x30 5012
S/U 0x30 5014
15-4
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 15-1. QSMCM Register Map
2
MSB
0
QSMCM Module Configuration Register (QSMCMMCR)
Dual SCI Interrupt Level (QDSCI_IL)
See Table 15-5 for bit descriptions.
Reserved
Reserved
See Section 15.5.1, "Port QS Data Register (PORTQS) for bit
MPC533 Reference Manual
See Table 15-7 for bit descriptions.
QSMCM Test Register (QTEST)
Queued SPI Interrupt Level (QSPI_IL)
See Table 15-6 for bit descriptions.
SCI1Control Register 0 (SCC1R0)
See Table 15-24 for bit descriptions.
SCI1Control Register 1 (SCC1R1)
See Table 15-25 for bit descriptions.
SCI1 Status Register (SC1SR)
See Table 15-26 for bit descriptions.
SCI1 Data Register (SC1DR)
See Table 15-27 for bit descriptions.
Reserved
Reserved
QSMCM Port Q Data Register (PORTQS)
descriptions.
LSB
15
Reserved
MOTOROLA