Motorola MPC533 Reference Manual page 497

Intermodule Bus
QADC Location
Intermodule Bus
QADC Location
Intermodule Bus
QADC Location
Byte access to an even address of a QADC64E location is shown in the top illustration of
Figure 13-24. In the case of write cycles, byte1 of the register is not disturbed. In the case
of a read cycle, the QADC64E provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of
Figure 13-24. In the case of write cycles, byte 0 of the register is not disturbed. In the case
of read cycles, the QADC64E provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest
illustration of Figure 13-24. The full 16 bits of data is written to and read from the
QADC64E location with each access.
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit
QADC64E locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit
read or write of an odd address. The second cycle is an 8-bit read or write of an even
address. The QADC64E address space is organized into 16-bit even address locations, so a
16-bit read or write of an odd address obtains or provides the lower half of one QADC64E
location, and the upper half of the following QADC64E location.
MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
W
Byte 0
Byte 0
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
W
Byte 0
Byte 0
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
W
BYTE 0
BYTE 0
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
Figure 13-24. Bus Cycle Accesses
R W
Byte 1
Byte 1
R W
Byte 1
Byte 1
R W
BYTE 1
BYTE 1
Digital Subsystem
R
R
R
QADC64E Bus CYC ACC
13-53