Motorola MPC533 Reference Manual page 546

Programming the QADC64E Registers
14.3.8 Status Registers (QASR0 and QASR1)
The status registers contains information about the state of each queue and the current A/D
conversion. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger
overrun bits (TOR1 and TOR2), all of the status register fields contain read-only data. The
four flag bits and the two trigger overrun bits are cleared by writing a zero to the bit after
the bit was previously read as a one.
MSB 1
0
Field CF1 PF1 CF2
SRESET
Addr
Bits Name
0 CF1
14-22
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
PF2 TOR1 TOR2
0000_0000_0000_0000
Figure 14-11. Status Register 0 (QASR0)
Table 14-13. QASR0 Bit Descriptions
Queue 1 Completion Flag — CF1 indicates that a queue 1 scan has been completed. The
scan completion flag is set by the QADC64E when the input channel sample requested by
the last CCW in queue 1 is converted, and the result is stored in the result table.
The end-of-queue 1 is identified when execution is complete on the CCW in the location
prior to that pointed to by BQ2, when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF1 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register
(QADCINT). The software reads the completion flag during an interrupt service routine to
identify the interrupt request. The interrupt request is cleared when the software writes a
zero to the completion flag bit, when the bit was previously read as a one. Once set, only
software or reset can clear CF1.
CF1 is maintained by the QADC64E regardless of whether the corresponding interrupt is
enabled. The software polls for CF1 bit to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 1 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
MPC533 Reference Manual
6 7 8 9
QS
0x30 4810 (QASR0_A)
Description
10 11 12 13 14
CWP
MOTOROLA
LSB
15