Motorola MPC533 Reference Manual page 325

for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat burst of data (8 x 2
bytes) or a 16-beat burst of data (16 x 1 bytes).
9.5.2 Single Beat Transfer
During the data transfer phase, the data is transferred from master to slave (in write cycles)
or from slave to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than the
cycle following the address transfer phase. The master has to take into consideration the
"one dead clock cycle" switching between drivers to avoid electrical contentions. The
master can stop driving the data bus as soon as it samples the TA line asserted on the rising
edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising edge of
the CLKOUT in which the TA signal is sampled/asserted.
9.5.2.1 Single Beat Read Flow
The basic read cycle begins with bus arbitration, followed by the address transfer, then the
data transfer. The handshakes illustrated in the following flow and timing figures
(Figure 9-4, Figure 9-5, and Figure 9-6) are applicable to the fixed transaction protocol.
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Master
Chapter 9. External Bus Interface
Slave
1. Receive address
2. Return data
3. Assert transfer acknowledge (TA)
Bus Operations
9-9