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• Queue pointers indicate current location for each queue
• Automated queue modes initiated by
— External edge trigger
— Periodic/Interval timer, within QADC64E module
— Software command
— External gated trigger (queue 1 only)
• Single-scan or continuous-scan of queues
• 64 result registers in the QADC64E module
• Output readable in three formats
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
• Unused analog channels can be used as digital input/output signals
• Modulus prescaler can divide the system clock for the converter by two to 128
• Alternate reference input, with control in the conversion command word (CCW)
The analog section includes input signals, an analog multiplexer, and the sample and hold
circuits. The analog conversion is performed by the digital-to-analog converter (DAC)
resistor-capacitor array and a high-gain comparator.
The digital control section contains queue control logic to sequence the conversion process
and interrupt generation logic. Also included are the periodic/interval timer, control and
status registers, the conversion command word (CCW) table RAM, and the result table
RAM.
The bus interface unit (BIU) allows the QADC64E to operate with the applications
software through the IMB3 environment.
14.2.2
Memory Map
The QADC64E occupies one Kbyte, or 512 16-bit entries, of address space. Ten 16-bit
registers are control, port, and status registers, 64 16-bit entries are the CCW table, and 64
16-bit entries are the result table, and occupy 192 16-bit address locations because the result
data is readable in three data alignment formats.
The QADC64E module on the MPC533 has its own memory space. Table 14-1 shows the
memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Key Features, Overview and Quick Reference Diagrams
14-3
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