Motorola MPC533 Reference Manual page 1065

Table H-6. USIU (Unified System Interface Unit) (continued)
Address Access
0x2F C100 U
0x2F C104 U
0x2F C108 U
0x2F C10C U
0x2F C110 U
0x2F C114 U
0x2F C118 U
0x2F C11C U
0x2F C120 – —
0x2F C13C
0x2F C140 U
0x2F C144 U
0x2F C148 – —
0x2F C174
0x2F C178 U
3
0x2F C200 U
3
0x2F C204 U
3
0x2F C208 U
0x2F C20C – —
0x2F C21C
4
0x2F C220 U
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Symbol
Memory Controller Registers
BR0 Base Register 0.
See Table 10-9 for bit descriptions.
OR0 Option Register 0.
See Table 10-11 for bit descriptions.
BR1 Base Register 1.
See Table 10-9 for bit descriptions.
OR1 Option Register 1.
See Table 10-11 for bit descriptions.
BR2 Base Register 2.
See Table 10-9 for bit descriptions.
OR2 Option Register 2.
See Table 10-11 for bit descriptions.
BR3 Base Register 3.
See Table 10-9 for bit descriptions.
OR3 Option Register 3.
See Table 10-11 for bit descriptions.
— Reserved
DMBR Dual-Mapping Base Register.
See Table 10-12 for bit descriptions.
DMOR Dual-Mapping Option Register.
See Table 10-13 for bit descriptions.
— Reserved
MSTAT Memory Status.
See Table 10-8 for bit descriptions.
System Integration Timers
TBSCR Time Base Status and Control.
See Table 6-18 for bit descriptions.
TBREF0 Time Base Reference 0.
See Section 6.2.2.4.3, "Time Base Reference
Registers (TBREF0 and TBREF1)" for bit
descriptions.
TBREF1 Time Base Reference 1.
See Section 6.2.2.4.3, "Time Base Reference
Registers (TBREF0 and TBREF1) for bit
descriptions.
— Reserved
RTCSC Real-Time Clock Status and Control.
See Table 6-19 for bit descriptions.
Appendix H. Internal Memory Map
Register Size Reset
32 H
32 H
32 H
32 H
32 H
32 H
32 H
32 H
— —
32 H
32 H
— —
16 H
16 H
32 U
32 U
— —
16 H
H-7