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10.3 Chip-Select Timing
The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface
between the MPC533 and external SRAM, EPROM, EEPROM, ROM peripherals. When
an address and address type match the values programmed in the BR and OR for one of the
memory controller banks, the attributes for the memory cycle are taken from the OR and
BR registers. These attributes include the following fields: CSNT, ACS, SCY, BSCY, WP,
TRLX, BI, PS, and SETA. Table 10-2 summarizes the chip-select timing options.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is written
to or read from memory. An output enable (OE) signal is provided to eliminate external
glue logic for read cycles. Upon system reset, a global (boot) chip select is available. (Refer
to Section 10.7, "Global (Boot) Chip-Select Operation" for more information on the global
chip select.) This provides a boot ROM chip select before the system is fully configured.
Timing Attribute
Access speed
Intercycle space time
Synchronous or
asynchronous device
Wait states
When a bank is configured for TA to be generated externally
(SETA bit is set) and the TRLX is set, the memory controller
requires the external device to provide at least one wait state
before asserting TA to complete the transfer. In this case, the
minimum transfer time is three clock cycles.
The internal TA generation mode is enabled if the SETA bit in the OR register is cleared.
However, if the TA signal is asserted externally at least two clock cycles before the wait
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 10-2. Timing Attributes Summary
Bits/Fields
TRLX
The TRLX (timing relaxed) bit determines strobe timing to be fast or
relaxed.
EHTR
The EHTR (extended hold time on read accesses) bit is provided for
devices that have long disconnect times from the data bus on read
accesses. EHTR specifies whether the next cycle is delayed one clock
cycle following a read cycle, to avoid data bus contentions. EHTR
applies to all cycles following a read cycle except for another read cycle
to the same region.
ACS, CSNT
The ACS (address-to-chip-select setup) and CSNT (chip-select negation
time) bits cause the timing of the strobes to be the same as the address
bus timing, or cause the strobes to have setup and hold times relative to
the address bus.
SCY, BSCY,
From zero to 15 wait states can be programmed for any cycle that the
SETA, TRLX
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set (2 +
(SCY x 2)).
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
NOTE
Chapter 10. Memory Controller
Chip-Select Timing
Description
10-11
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