Motorola MPC533 Reference Manual page 512

QADC64E Integration Requirements
Port A signals are configured as inputs or outputs by programming the port data direction
register, DDRQA. The digital input signal states are read from the port data register,
PORTQA, when the port data direction register specifies that the signals are inputs. The
digital data in the port data register is driven onto the Port A signals when the corresponding
bit in the port data direction register specifies that the signals are outputs. Refer to
Appendix A, "Internal Memory Map" for more information. Since the outputs are
configured as push-pull drivers, external pull-up provisions are not necessary when the
output is used to drive another integrated circuit.
13.7.2 External Trigger Input Signals
The QADC64E uses two external trigger signals (ETRIG[2:1]). Each of the two input
external trigger signals is associated with one of the scan queues, queue 1 or queue 2. The
assignment of ETRIG[2:1] to a queue is made in the QACR0 register by the TRG bit. When
TRG=0, ETRIG[1] triggers queue 1 and ETRIG[2] triggers queue 2. When TRG=1,
ETRIG[1] triggers queue 2 and ETRIG[2] triggers queue 1.
13.7.3 Analog Power Signals
V and V signals supply power to the analog subsystems of the QADC64E module.
DDA SSA
Dedicated power is required to isolate the sensitive analog circuitry from the normal levels
of noise present on the digital power supply. Refer to Appendix E, "Electrical
Characteristics" for more information.
The analog supply signals (V
voltages (V and V
RH
the analog input circuitry.
13-68
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
and V
DDA
) and of the analog multiplexer inputs. Figure 13-47 is a diagram of
RL
MPC533 Reference Manual
) define the limits of the analog reference
SSA
MOTOROLA