Motorola MPC533 Reference Manual page 789

Each MIRSM includes:
• One 16-bit status register (for the flags)
• One 16-bit enable register for each implemented level
• One 16-bit IRQ pending register for each implemented level
One bit position in each of the above registers is associated with one submodule.
If a submodule in a group of 16 cannot generate interrupts, then
its corresponding flag bit in the status register is inactive and is
read as zero.
When an event occurs in a submodule that activates a flag line, the corresponding flag bit
in the status register is set. The status register is read/write, but a flag bit can be reset only
if it has previously been read as a one. Writing a "one" to a flag bit has no effect. When the
software intends to clear only one flag bit within a status register, the software must write
an all-ones 16-bit value except for the bit position to be cleared which is a zero.
The enable register is initialized by the software to indicate whether each interrupt request
is enabled for the levels defined in the ICS.
In the case of multiple requests levels implementation in the
same MIOS14, it is possible to enable interrupts at more than
one different levels for the same submodule. It is the
responsibility of the software to manage this.
Each bit in the IRQ pending register is the result of a logical "AND" between the
corresponding bits in the status and in the enable registers. If a flag bit is set and the level
enable bit is also set, then the IRQ pending bit is set, and the information is transferred to
the interrupt control section that is in charge of sending the corresponding level to the CPU.
The IRQ pending register is read only.
When the enable bit is not set for a particular submodule, the
corresponding status register bit is still set when the
corresponding flag is set. This allows the traditional software
approach of polling the flag bits to see which ones are set. The
status register makes flag polling easy, since up to 16 flag bits
are contained in one register.
MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
NOTE
NOTE
MIOS14 Interrupts
17-65