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transfer error acknowledge (TEA) is asserted internally by the MPC533, and RCPU access
is terminated with a data error, causing a machine check state or exception.
The bus monitor timing bit in the system protection control register (SYPCR[BMT])
defines the bus monitor time-out period. The programmability of the time-out allows for
variation in system peripheral response time. The timing mechanism is clocked by the
external bus clock divided by eight. The maximum value is 2040 system clock cycles.
SYPCR[BME] enables or disables the bus monitor. But regardless of the state of this bit the
bus monitor is always enabled when freeze is asserted in debug mode.
6.1.6
Decrementer (DEC)
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC533
architecture to provide a decrementer interrupt. This binary counter is clocked by the same
frequency as the time base (also defined by the MPC533 architecture). The operation of the
time base and decrementer are therefore coherent. The DEC is clocked by the TMBCLK
clock. The decrementer period is computed as follows:
The state of the DEC is not affected by any resets and should be initialized by software. The
DEC runs continuously after power-up once the time base is enabled by setting the TBE bit
of the TBSCR (see Table 6-18) (unless the clock module is programmed to turn off the
clock). The decrementer continues counting while reset is asserted.
Reading from the decrementer has no effect on the counter value. Writing to the
decrementer replaces the value in the decrementer with the value in the GPR.
Whenever bit 0 (the MSB) of the decrementer changes from zero to one, a decrementer
exception occurs. If software alters the decrementer such that the content of bit 0 is changed
to a value of 1, a decrementer exception occurs.
A decrementer exception causes a decrementer interrupt request to be pending in the
RCPU. When the decrementer exception is taken, the decrementer interrupt request is
automatically cleared.
Table 6-6 illustrates some of the periods available for the decrementer, assuming a 4-MHz
or 20-MHz crystal, and TBS = 0 which selects TMBCLK division to 4.
Time base must be enabled to use the decrementer. See
Section 6.2.2.4.4, "Time Base Control and Status Register
(TBSCR)," for more information.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
T
=
DEC
NOTE
Chapter 6. System Configuration and Protection
System Configuration and Protection Features
32
2
F
TMBCLK
6-19
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