Motorola MPC533 Reference Manual page 695

16.3.3 Bit Timing
The TouCAN module uses three 8-bit registers to set up the bit timing parameters required
by the CAN protocol. Control registers one and two (CANCTRL1, CANCTRL2) contain
the PROPSEG, PSEG1, PSEG2, and the RJW fields that allow configuration of the bit
timing parameters. The prescaler divide register (PRESDIV) allows selection of the ratio
used to derive the serial clock (S-clock) from the system clock. The time quanta clock
operates at the S-clock frequency. Table 16-8 provides examples of system clock, CAN bit
rate, and S-clock bit timing parameters, and Figure 16-5 shows the relationship between the
system clock and the CAN bit segments. Refer to Section 16.7, "Programmer's Model," for
more information on the bit timing registers.
SYSTEM
CLOCK
S-CLOCK
TIME
QUANTUM
SS
Transmit
point
SS
SYNC_SEG
Figure 16-5. Relationship between System Clock and CAN Bit Segments
A bit is divided into four separate non-overlapping time segments called SYNC_SEG,
PROPSEG, PSEG1, and PSEG2. These are illustrated in Figure 16-5. The period of the
nominal bit time (NBT) is the sum of the segment durations:
t = t
NBT SYNC_SEG
The sample point indicated in Figure 16-5 is the position of the actual sample point if a
single sample per bit is selected (CANCTRL1[SAMP] bit = 0). If three samples per bit are
selected, the sample point indicated in Figure 16-5 marks the position of the final sample.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Baud Rate Prescaler (PRESDIV)
PROPSEG
Nominal bit time (NBT)
+ t + t + t
PROPSEG PSEG1
Chapter 16. CAN 2.0B Controller Module
PSEG1 PSEG2
Sample point
PSEG2
TouCAN Architecture
16-9