Motorola MPC533 Reference Manual page 328

Bus Operations
9.5.2.2 Single Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then
the data transfer. The handshakes are illustrated in the following flow and timing diagrams
as applicable to the fixed transaction protocol.
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
Figure 9-7. Basic Flow Diagram of a Single Beat Write Cycle
9-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Master
1. Drive data
1. Interrupt data driving
MPC533 Reference Manual
Slave
1. Assert transfer acknowledge (TA)
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