Motorola MPC533 Reference Manual page 641

C2
Is this the
Last Command
in the Queue?
N
Increment Working
Queue Pointer
Is HALT
or FREEZE
Asserted?
N
A2
Figure 15-23. Flowchart of QSPI Slave Operation (Part 2)
Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the
SPI bus master supplies the clock signal SCK to time the transfer of data. Four possible
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Y
Y
Chapter 15. Queued Serial Multi-Channel Module
Queued Serial Peripheral Interface
Set SPIF
Status Flag
Is Interrupt
Y
Enable Bit
SPIFIE Set?
N
Is Wrap
Y
Enable Bit
Asserted?
N
Disable QSPI
A2
Halt QSPI and
Set HALTA
Is Interrupt
Y
Enable Bit
HMIE Set?
N
Is HALT
Y
Or FREEZE
Asserted?
N
Request Interrupt
Reset Working Queue
Pointer To NEWQP or 0x0000
Request Interrupt
QSPI SLV2 FLOW6
15-35