Motorola MPC533 Reference Manual page 465

Table 13-9. QASR0 Bit Descriptions (continued)
Bits Name
2 CF2
3 PF2
MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Queue 2 Completion Flag — CF2 indicates that a queue 2 scan has been completed. CF2
is set by the QADC64E when the input channel sample requested by the last CCW in queue
2 is converted, and the result is stored in the result table.
The end-of-queue 2 is identified when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF2 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register
(QADCINT). The software reads CF2 during an interrupt service routine to identify the
interrupt request. The interrupt request is cleared when the software writes a zero to the
CF2 bit, when the bit was previously read as a one. Once set, only software or reset can
clear CF2.
CF2 is maintained by the QADC64E regardless of whether the corresponding interrupts are
enabled. The software polls for CF2 to see if it is set. This allows the software to recognize
that the QADC64E is finished with a queue 2 scan. The software acknowledges that it has
detected the completion flag being set by writing a zero to the completion flag after the bit
was read as a one.
Queue 2 Pause Flag — PF2 indicates that a queue 2 scan has reached a pause. PF2 is
set by the QADC64E when the current queue 2 CCW has the pause bit set, the selected
input channel has been converted, and the result has been stored in the result table.
Once PF2 is set, the queue enters the paused state and waits for a trigger event to allow
queue execution to continue. However, if the CCW with the pause bit set is the last CCW
in a queue, the queue execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception occurs in software
controlled mode, where the PF2 can be set but queue 2 never enters the pause state.
When PF2 is set and interrupts are enabled for the corresponding queue, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register. The
software reads PF2 during an interrupt service routine to identify the interrupt request. The
interrupt request is cleared when the software writes a zero to PF2, when the bit was
previously read as a one. Once set, only software or reset can clear PF2.
PF2 is maintained by the QADC64E regardless of whether the corresponding interrupts are
enabled. The software may poll PF2 to find out when the QADC64E has reached a pause
in scanning a queue. The software acknowledges that it has detected a pause flag being
set by writing a zero to PF2 after the bit was last read as a one.
0 = queue 2 has not reached a pause
1 = queue 2 has reached a pause
Refer to Table 13-10 for a summary of pause response in all scan modes.
Programming the QADC64E Registers
Description
13-21