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PLL and Clock Oscillator External Components Layout Requirements
Smaller C
makes the PLL faster to gain lock but less stable. Higher C
XFC
PLL more stable but slower to gain lock. Because each board layout and application is
unique, C
must be evaluated in a system.
XFC
The minimum required value (including capacitor tolerance) for C
following two cases:
0 < (MF+1) < 4
(MF+1) >= 4
MF is the multiplication factor in the PLPRCR register (refer to Section 8.11.2, "PLL,
Low-Power, and Reset-Control Register (PLPRCR)" for more information).
I.4
PLL and Clock Oscillator External Components
Layout Requirements
I.4.1
Traces and Placement
Traces connecting capacitors, crystal, resistor should be as short as possible. Therefore, the
components (crystal, resistor and capacitors) should be placed as close to the oscillator pins
of the MPC533 as possible.
The voltage to the VDDSYN pin should be well regulated and the pin should be provided
with an extremely low impedance path from the VDDSYN filter to the VDDSYN pad.
The VSSSYN pin should be provided with an extremely low impedance path in the board.
All the filters for the supplies should be located as close as possible to the chip package. It
is recommended to design individual VSSSYN plane to improve VSSSYN quietness.
I.4.2
Grounding/Guarding
The traces from the oscillator pins and PLL pins of the MPC533 should be guarded from
all other traces to reduce crosstalk. It can be provided by keeping other traces away from
the oscillator circuit and placing a ground plane around the components and traces.
I-6
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Board
CXFC
Figure I-7. PLL Off-Chip Capacitor Example
MPC533 Reference Manual
C
= (1130 * (MF+1) – 80) pF
XFC
C
= (2100 * (MF+1)) pF
XFC
MPC53x Device
XFC
VDDSYN
makes the
XFC
is determined by the
XFC
MOTOROLA
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