Motorola MPC533 Reference Manual page 319

The read/write (RD/WR) signal determines the direction of the transfer during a bus cycle.
Driven at the beginning of a bus cycle, RD/WR is valid at the rising edge of the clock in
which TS is asserted. The logic level of RD/WR only changes when a write cycle is
preceded by a read cycle or vice versa. The signal may remain low for consecutive write
cycles.
Bus
Interface
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
ADDR[8:31]
24
RD/WR
1
BURST
1
TSIZ[0:1]
2
AT[0:3]
4
PTR
1
BDIP
1
TS
1
RSV
1
KR
1
CR
1
DATA[0:31]
32
BI / STS
1
TA
1
TEA
1
BR
1
BG
1
BB
1
RETRY
1
Figure 9-2. MPC533 Bus Signals
Chapter 9. External Bus Interface
Bus Control Signals
Address
and
Transfer
Attributes
Transfer
Start
Reservation
Protocol
Data
Transfer
Cycle
Termination
Arbitration
9-3