Motorola MPC533 Reference Manual page 642

Queued Serial Peripheral Interface
combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in
SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but can be set to any value from eight to sixteen bits by writing
a value into the BITS field in SPCR0 and setting BITSE in command RAM.
Typically, SPI bus outputs are not open drain unless multiple SPI masters are in the system.
If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open drain outputs.
An external pull-up resistor should be used on each output line. WOMQ affects all QSPI
pins regardless of whether they are assigned to the QSPI or used as general-purpose I/O.
15.6.5 Master Mode Operation
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the QSPI
can initiate serial transfers, but cannot respond to externally initiated transfers. When the
slave select input of a device configured for master mode is asserted, a mode fault occurs.
Before QSPI operation begins, PQSPAR must be written to assign the necessary pins to the
QSPI. The pins necessary for master mode operation are MISO, MOSI, SCK, and one or
more of the chip-select pins. MISO is used for serial data input in master mode, and MOSI
is used for serial data output. Either or both may be necessary, depending on the particular
application. SCK is the serial clock output in master mode and must be assigned to the QSPI
for proper operation.
The PORTQS data register must next be written with values that make the QGPIO6/SCK
(bit 13 QDSCK of PORTQS) and QGPIO[3:0]/PCS[3:0] (bits 12:9 QDPCS[3:0] of
PORTQS) outputs inactive when the QSPI completes a series of transfers. Pins allocated to
the QSPI by PQSPAR are controlled by PORTQS when the QSPI is inactive. PORTQS I/O
pins driven to states opposite those of the inactive QSPI signals can generate glitches that
momentarily enable or partially clock a slave device.
For example, if a slave device operates with an inactive SCK state of logic one (CPOL = 1)
and uses active low peripheral chip-select PCS0, the QDSCK and QDPCS0 bits in
PORTQS must be set to 0b11. If QDSCK and QDPCS0 = 0b00, falling edges will appear
on QGPIO6/SCK and GPIO0/PCS0 as the QSPI relinquishes control of these pins and
PORTQS drives them to logic zero from the inactive SCK and PCS0 states of logic one.
Before master mode operation is initiated, QSMCM register DDRQS is written last to
direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate
chip-select pins PCS[3:0] as outputs. The MISO pin must be configured as an input.
After pins are assigned and configured, write appropriate data to the command queue. If
data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as
appropriate.
15-36 MPC533 Reference Manual MOTOROLA
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