Motorola MPC533 Reference Manual page 664

Serial Communication Interface
automatically cleared. The processor must clear it by first reading SCxSR while TC is set,
then writing new data to SCxDR, or writing to SCTQ[0:15] for transmit queue operation.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is
transmitted as a preamble to the following data frame. If TC = 0, the current operation
continues until the final bit in the frame is sent, then the preamble is transmitted. The TC
bit is set at the end of preamble transmission.
The SBK bit in SCCxR1 is used to insert break frames in a transmission. A non-zero integer
number of break frames are transmitted while SBK is set. Break transmission begins when
SBK is set, and ends with the transmission in progress at the time either SBK or TE is
cleared. If SBK is set while a transmission is in progress, that transmission finishes
normally before the break begins. To ensure the minimum break time, toggle SBK quickly
to one and back to zero. The TC bit is set at the end of break transmission. After break
transmission, at least one bit-time of logic level one (mark idle) is transmitted to ensure that
a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and
TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames
are transmitted. The TC flag is set, and control of the TXD pin reverts to PQSPAR and
DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing data in the
buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output, then write a one to either
QDTX1 or QDTX2 of the PORTQS register. See Section 15.5.1, "Port QS Data Register
(PORTQS)." When the transmitter releases control of the TXD pin, it reverts to driving a
logic one output.
To insert a delimiter between two messages, to place non-listening receivers in wake-up
mode between transmissions, or to signal a re-transmission by forcing an idle-line, clear
and then set TE before data in the serial shifter has shifted out. The transmitter finishes the
transmission, then sends a preamble. After the preamble is transmitted, if TDRE is set, the
transmitter marks idle. Otherwise, normal transmission of the next sequence begins.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit
interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits in SCCxR1.
Service routines can load the last data frame in a sequence into SCxDR, then terminate the
transmission when a TDRE interrupt occurs.
15-58 MPC533 Reference Manual MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE