Motorola MPC533 Reference Manual page 190

Exception Table Relocation (ETR)
The 8 Kbytes allocated for the original PowerPC exception
table can be almost fully utilized. This is possible if the
MPC533 system memory is NOT mapped to the exception
address space, (i.e., the addresses 0xFFF0_0000 to
0xFFF0_1FFF are not used).
In such case, these 8 Kbytes can fully be utilized by the
compiler, except for the lower 64 words (256 bytes) which are
dedicated for the branch instructions.
If the RCPU, while executing an exception, issues any address
between
0xFFF0_0104), then the operation of the MPC533 is not
guaranteed if the ETR is enabled.
In order to activate the exception table relocation feature, the following steps are required:
1. Set the RCPU MSR[IP] bit
2. Set the BBCMCR[ETRE] bit. See Section 4.6.2.1, "BBC Module Configuration
Register (BBCMCR)," for programming details.
3. Program the BBCMCR[OERC] bits to determine the exception branch table
location in the memory, according the description in Table 4-2.
The ETR feature can be activated from reset, by setting corresponding bits in the reset
configuration word.
.
Name of Exception
System Reset
Machine Check
Data Storage
2
External Interrupt
Alignment
Program
Floating Point unavailable
Decrementer
System Call
Trace
Floating Point Assist
4-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
two successive
Table 4-1. Exception Addresses Mapping
Original Address Issues by
Core
0xFFF 0100
0xFFF0 0200
0xFFF0 0300
0xFFF0 0500
0xFFF0 0600
0xFFF0 0700
0xFFF0 0800
0xFFF0 0900
0xFFF0 0C00
0xFFF0 0D00
0xFFF0 0E00
MPC533 Reference Manual
exception entries
Mapped Address by Exception Table
Relocation Logic
Compression disabled
1
Page_Offset +0x08
Page_Offset+0x010
Page_Offset+0x018
Page_Offset+0x028
Page_Offset+0x030
Page_Offset+0x038
Page_Offset+0x040
Page_Offset+0x048
Page_Offset+0x060
Page_Offset+0x068
Page_Offset+0x070
(e.g.,
Compression enabled
1
Page_Offset +0x0B8
MOTOROLA