Motorola MPC533 Reference Manual page 992

Data Trace
provided the address ranges are enabled in either DTA register, are candidates to be
transmitted. Data read and/or data write trace may be enabled via the TA field of the data
trace attributes registers (DTA).
Data trace ranges are word aligned. Therefore, the address
range fields (DTEA and DTSA) of the DTA registers are only
23 bits wide and, as such, should be assigned by the tool with
the 23 most significant bits of the intended 25-bit range
address, i.e. the 2 LSB of the address are not used.)
The off-core MPC500 special purpose register (SPR) map
cannot be distinguished from the normal memory map accesses
via the defined address range control. If data trace ranges are
set up such that the off-core MPC500 SPR map falls within
active ranges, then accesses to these off-core MPC500 SPRs
will be traced, and the messages will not be distinguishable
from accesses to normal memory map space. Off-core
MPC500 SPRs typically exist in the 8-Kbyte – 16-Kbyte
lowest memory block (0x2000 - 0x3FF0). If data or peripherals
are mapped to this space, load/stores to MPC500 SPRs will be
indistinguishable from data or peripheral accesses.
22.4.6 Special L-Bus Cases
Special L-bus cases are handled as described in Table 22-30.
L-bus Cycle Aborted
L-bus Cycle with data error
L-bus Cycle terminated due to address error
L-bus Cycle completed without error
L-bus Cycle initiated by READI (Read/Write Access)
L-bus Cycle is an instruction fetch
Data Storage Interrupt
System Reset
22-60
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
NOTE
Table 22-30. Special L-Bus Case Handling
Special Case
MPC533 Reference Manual
Action
Cycle ignored
Message discarded
Cycle ignored
Cycle captured and transmitted
Cycle ignored
Cycle ignored
Cycle ignored
Cycle ignored
MOTOROLA