Motorola MPC533 Reference Manual page 671

Table 15-32. QSCI1CR Bit Descriptions (continued)
Bits Name
8 — Reserved
9 QTE Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be
ignored by software. The TC bit is redefined to indicate when the entire queue is finished
transmitting. When clear, the SCI1 functions as described in the previous sections and the bits
related to the queue (Section 5.5 and its subsections) should be ignored by software with the
exception of QTE.
0 = Transmit queue is disabled
1 = Transmit queue is enabled
10 QRE Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be
ignored by software. When clear, the SCI1 functions as described in the previous sections and
the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with
the exception of QRE.
0 = Receive queue is disabled
1 = Receive queue is enabled
11 QTWE Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from
the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE
is cleared by hardware.
0 = Transmit queue wrap feature is disabled
1 = Transmit queue wrap feature is enabled
12:15 QTSZ Queue transfer size. The QTSZ bits allow programming the number of data frames to be
transmitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified.
QTSZ is loaded into QPEND initially or when a wrap occurs.
15.8.2.2 QSCI1 Status Register (QSCI1SR)
MSB 1
0
Field —
SRESET 000
Addr
Figure 15-32. QSCI1 Status Register (QSCI1SR)
Bits Name
0:2 — Reserved
3 QOR Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred
from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data
transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid.
Additional data received during a queue overrun condition is not lost provided the receive queue
is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received
in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the
OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
0 = The queue is empty before valid data is in the SC1DR
1 = The queue is not empty when valid data is in the SC1DR
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
QOR QTHF QBHF QTHE QBHE
0 1 1
Table 15-33. QSCI1SR Bit Descriptions
Chapter 15. Queued Serial Multi-Channel Module
Description
6 7 8 9
QRPNT
1 1 0000
0x30 502A
Description
SCI Queue Operation
10 11 12 13 14
QPEND
0000
LSB
15
15-65