Motorola MPC533 Reference Manual page 709

16.7 Programmer's Model
Table 16-10 shows the TouCAN address map. Refer to Figure 1-2 to locate each TouCAN
module in the MPC533 address map.
The column labeled "Access" indicates the privilege level at which the CPU must be
operating to access the register. A designation of "S" indicates that supervisor mode is
required. A designation of "S/U" indicates that the register can be programmed for either
supervisor mode access or unrestricted access.
The address space for each TouCAN module is split, with 128 bytes starting at the base
address, and an extra 256 bytes starting at the base address +128. The upper 256 are fully
used for the message buffer structures. Of the lower 128 bytes, some are not used. Registers
with bits marked as "reserved" should always be written as logic 0.
Typically, the TouCAN control registers are programmed during system initialization,
before the TouCAN becomes synchronized with the CAN bus. The configuration registers
can be changed after synchronization by halting the TouCAN module. This is done by
setting the HALT bit in the TouCAN module configuration register (CANMCR). The
TouCAN responds by asserting the CANMCR NOTRDY bit. Additionally, the control
registers can be modified while the MCU is in background debug mode.
The TouCAN has no hard-wired protection against invalid
bit/field programming within its registers. Specifically, no
protection is provided if the programming does not meet CAN
protocol requirements.
Access Address
S 0x30 7480(B)
S 0x30 7482(B)
S 0x30 7484(B)
S/U 0x30 7486(B)
S/U 0x30 7488(B)
S/U 0x30 748A(B)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
Table 16-10. TouCAN Register Map
MSB
0
TouCAN Module Configuration Register (CANMCR_B)
Control Register 0 (CANCTRL0_B))
See Table 16-13 and Table 16-16 for
bit descriptions.
Control and Prescaler
Divider Register (PRESDIV_B))
See Table 16-17 and Table 16-18 for
bit descriptions.
Chapter 16. CAN 2.0B Controller Module
See Table 16-11 for bit descriptions.
TouCAN Test Register (CANTCR_B))
.
TouCAN Interrupt Register (CANICR_B))
See Table 16-12 for bit descriptions.
Control Register 1 (CANCTRL1_B))
See Table 16-16 for bit descriptions.
Control Register 2 (CANCTRL2_B))
See Table 16-18 for bit descriptions.
Free-Running Timer Register (TIMER_B))
See Table 16-19 for bit descriptions.
Programmer's Model
LSB
15
16-23