Motorola MPC533 Reference Manual page 540

Programming the QADC64E Registers
Table 14-8 displays the bits in PRESCALER field which enable a range of QCLK
frequencies
Table 14-8. Prescaler f
Prescaler f
SYSCLK
[6:0] Div
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
14-16
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Prescaler f
SYSCLK
[6:0] Div
2 0100000 33
2 0100001 34
3 0100010 35
4 0100011 36
5 0100100 37
6 0100101 38
7 0100110 39
8 0100111 40
9 0101000 41
10 0101001 42
11 0101010 43
12 0101011 44
13 0101100 45
14 0101101 46
15 0101110 47
16 0101111 48
17 0110000 49
18 0110001 50
19 0110010 51
20 0110011 52
21 0110100 53
22 0110101 54
23 0110110 55
24 0110111 56
25 0111000 57
26 0111001 58
27 0111010 59
28 0111011 60
29 0111100 61
30 0111101 62
MPC533 Reference Manual
Divide-by Values
SYSCLK
Prescaler f
SYSCLK
[6:0] Div
1000000 65
1000001 66
1000010 67
1000011 68
1000100 69
1000101 70
1000110 71
1000111 72
1001000 73
1001001 74
1001010 75
1001011 76
1001100 77
1001101 78
1001110 79
1001111 80
1010000 81
1010001 82
1010010 83
1010011 84
1010100 85
1010101 86
1010110 87
1010111 88
1011000 89
1011001 90
1011010 91
1011011 92
1011100 93
1011101 94
Prescaler f
SYSCLK
[6:0] Div
1100000 97
1100001 98
1100010 99
1100011 100
1100100 101
1100101 102
1100110 103
1100111 104
1101000 105
1101001 106
1101010 107
1101011 108
1101100 109
1101101 110
1101110 111
1101111 112
1110000 113
1110001 114
1110010 115
1110011 116
1110100 117
1110101 118
1110110 119
1110111 120
1111000 121
1111001 122
1111010 123
1111011 124
1111100 125
1111101 126
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