Motorola MPC533 Reference Manual page 943

RCPU Nexus
Name
Bits Bits
0 7 DOR
1 6 DME
3:5 4:2 TM
6:7 1:0 EC
1
The DOR and DME fields in the DC register can only be modified when system reset is asserted, or reset (to default
state) when the READI module is reset by the assertion of RSTI.
Table 22-8 describes the DC register fields with the mode configurations for RCPU
development access.
Table 22-8. RCPU Development Access Modes
DOR DME
x x
x 0
0 1
1 1
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 22-7. DC Bit Descriptions
1
READI Debug Mode Entry Out-of-reset Field can be configured to enable or disable
debug mode entry out of reset.
0 Debug Mode Not Entered Out-of-Reset
1 Debug Mode Entered Out-of-Reset
1
READI Debug Mode Enable Field can be configured to enable or disable debug mode.
0 Debug Mode Disabled
1 Debug Mode Enabled
READI Trace Mode Field can be configured to enable BTM, DTM, and OTM. Any or
all types of trace may be enabled.
000 No Trace
1xx BTM Branch Trace Messaging Enabled
x1x DTM Data Trace Messaging Enabled
xx1 OTM Ownership Trace Messaging Enabled
READI EVTI Control Field can be configured for synchronization and breakpoint
generation. If the EC is equal to 0b00, asserting EVTI will cause the next program and
data trace message to be a synchronization message (providing program and data
trace are enabled). If the EC field is equal to 0b01, a breakpoint will be generated. If
the field is configured to one of the reserved states, its action reverts to that of the
default state.
NOTE: The EVTI signal is level sensitive when EC is configured for breakpoint
generation. This implies that as long as EVTI assertion is continued (with EC set to
0b01), the READI module will continue requesting a breakpoint. The user must detect
breakpoint generation and negate the EVTI signal appropriately.
00 EVTI for program and data trace synchronization
01 EVTI for breakpoint generation
1x No Action
DPA
0 No RCPU Development Access via READI. RCPU access is done through
BDM signals.
1 Non-debug mode access of RCPU development through READI.
1 Debug mode is enabled through READI (RCPU is still in normal mode, out
of reset)
1 Debug mode is enabled through READI and entered out-of-reset. Debug
mode entry causes RCPU to halt.
Chapter 22. READI Module
Description
RCPU Development Access through READI
Programming Model
22-11