Motorola MPC533 Reference Manual page 139

Table 3-12. Machine State Register Bit Descriptions
Bits Name
0:12 — Reserved
13 POW Power management enable.
0 Power management disabled (normal operation mode)
1 Power management enabled (reduced power mode)
14 — Reserved
15 ILE Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception. Little-endian mode is not
supported on the MPC533. This bit should be cleared to 0 at all times.
0 The processor runs in big-endian mode during exception processing.
1 The processor runs in little-endian mode during exception processing.
16 EE External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts in the CPU core prior to masking or disabling any interrupt
which might be currently pending at the CPU core. For external interrupts, it is recommended
that the edge-triggered interrupt scheme be used. After disabling an interrupt, sufficient time
should be allowed for the negated signal to propagate to the RCPU core, prior to re-enabling
interrupts. For an interrupt generated from an IMB3 module, 6 clocks is sufficient (for IMBCLK
in 1:1 mode). 0The processor delays recognition of external interrupts and decrementer
exception conditions.
1 The processor is enabled to take an external interrupt or the decrementer exception.
17 PR Privilege level.
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
18 FP Floating-point available .
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
1 The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19 ME Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20 FE0 Floating-point exception mode 0 (See Table 3-13.)
21 SE Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception. Single-step
tracing may not be present on all implementations.
22 BE Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
23 FE1 Floating-point exception mode 1 (See Table 3-13).
24 — Reserved
25 IP Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 3. Central Processing Unit
Description
OEA Register Set
3-23