Motorola MPC533 Reference Manual page 222

System Configuration and Protection Features
Figure 6-2 illustrates the functionality of the SGPIO.
Internal
Bus
GPIO
Write
Register
Read
Write
Clock
Path of Write Operation
Path of Read Operation
SGPIO Circuitry
Figure 6-2. Circuit Paths of Reading and Writing to SGPIO
6.1.4 Enhanced Interrupt Controller
6.1.4.1 Key Features
• Significant interrupt latency reduction from that of the MPC555.
• Simplified interrupt structure
• Up to 48 different interrupt requests
• Splitting of single external interrupt vector into up to 48 vectors, one for each source
• Automatic lower priority requests masking
• Full backward compatibility with MPC555/MPC556 (enhanced mode is software
programmable.)
6.1.4.2 Interrupt Configuration
An overview of the MPC533 interrupt structure is shown in Figure 6-5. The interrupt
controller receives interrupts from USIU internal sources, such as PIT, RTC, from the
6-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Read Path
Write Path
MPC533 Reference Manual
GPIO
Read
Register
OE
Write
Read
MOTOROLA
SGPIO
Pad