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Signal Name
PTR
Program trace
BDIP
Burst data in progress
TS
Transfer start
CR
Cancel reservation
KR
Kill reservation
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-1. MPC533 SIU Signals (continued)
Pins
Active
1
High
1
Low
Transfer Start
1
Low
Reservation Protocol
1
Low
1
Low
Chapter 9. External Bus Interface
Bus Interface Signal Descriptions
I/O
O
Driven by the MPC533 along with the address when it
owns the external bus. Indicates additional information
about the address on the current transaction.
I
Only for testing purposes.
O
Driven by the MPC533 when it owns the external bus.
It is part of the burst protocol. When BDIP is asserted,
the second beat in front of the current one is requested
by the master. This signal is negated prior to the end
of a burst to terminate the burst data phase early.
I
Driven by an external master when it owns the external
bus. When BDIP is asserted, the second beat in front
of the current one is requested by the master. This
signal is negated prior to the end of a burst to
terminate the burst data phase early. The MPC533
does not support burst accesses to internal slaves.
O
Driven by the MPC533 when it owns the external bus.
Indicates the start of a transaction on the external bus.
I
Driven by an external master when it owns the external
bus. It indicates the start of a transaction on the
external bus or (in show cycle mode) signals the
beginning of an internal transaction.
Each MPC500 CPU has its own CR signal. Assertion
I
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX instruction
issued by the RCPU to a non-local bus on which the
storage reservation
I
by the non-local bus interface to back-off the cycle.
Refer to Section 9.5.10, "Storage Reservation" for
details.
Description
has been lost, this signal is used
9-5
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