Motorola MPC533 Reference Manual page 670

SCI Queue Operation
transmit and receive operations done via SC1DR). However, if the SCI1 queue feature is
enabled (by setting the QTE and/or QRE bits within QSCI1CR) a set of 16 entry queues is
allocated for the receive and/or transmit operation. Through software control the queue is
capable of continuous receive and transfer operations within the SCI1 serial unit.
15.8.2 Queued SCI1 Status and Control Registers
The SCI1 queue uses the following registers:
• QSCI1 control register (QSCI1CR, address offset 0x28)
• QSCI1 status register (QSCI1SR, address offset 0x2A)
15.8.2.1 QSCI1 Control Register (QSCI1CR)
MSB 1 2
0
Field QTPNT
SRESET
Addr
Figure 15-31. QSCI1 Control Register (QSCI1CR)
Bits Name
0:3 QTPNT Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the
transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field
is writable in test mode only; otherwise it is read-only.
4 QTHFI Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the
QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the
queue locations SCRQ[0:7].
0 = QTHF interrupt inhibited
1 = Queue top-half full (QTHF) interrupt enabled
5 QBHFI Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever
the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to
the queue locations SCRQ[8:15].
0 = QBHF interrupt inhibited
1 = Queue bottom-half full (QBHF) interrupt enabled
6 QTHEI Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt
whenever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit
refers to the queue locations SCTQ[0:7].
0 = QTHE interrupt inhibited
1 = Queue top-half empty (QTHE) interrupt enabled
7 QBHEI Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt
whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This bit
refers to the queue locations SCTQ[8:15].
0 = QBHE interrupt inhibited
1 = Queue bottom-half empty (QBHE) interrupt enabled
15-64
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3 4 5 6
QTHFI QBHFI QTHEI QBHEI
0000_0000_0000_0000
Table 15-32. QSCI1CR Bit Descriptions
MPC533 Reference Manual
7 8 9 10
— QTE QRE QTWE
0x30 5028
Description
11 12 13 14 LSB
15
QTSZ
MOTOROLA