Motorola MPC533 Reference Manual page 157

found, the instruction is accepted by the appropriate execution unit, and the data
found in the destination register is copied to the history buffer. If a data dependency
exists, the machine is stalled until the dependency is resolved.
2. In the execute stage, each execution unit that has an executable instruction executes
the instruction. (For some instructions, this occurs over multiple cycles.)
3. In the writeback stage, the execution unit writes the result to the destination register
and reports to the history buffer that the instruction is completed.
4. In the retirement stage, the history buffer retires instructions in architectural order.
An instruction retires from the machine if it completes execution with no
exceptions and if all instructions preceding it in the instruction stream have finished
execution with no exceptions. As many as six instructions can be retired in one
clock.
The history buffer maintains the correct architectural machine state. An exception is taken
only when the instruction is ready to be retired from the machine (i.e., after all
previously-issued instructions have already been retired from the machine). When an
exception is taken, all instructions following the excepting instruction are canceled, (i.e.,
the values of the affected destination registers are restored using the values saved in the
history buffer during the dispatch stage).
Figure 3-22 shows basic instruction pipeline timing.
FETCH
DECODE
READ AND EXECUTE
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
Table 3-22 indicates the latency and blockage for each type of instruction. Latency refers
to the interval from the time an instruction begins execution until it produces a result that
is available for use by a subsequent instruction. Blockage refers to the interval from the
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
i1 i2
i1
i1
i1
Figure 3-22. Basic Instruction Pipeline
Chapter 3. Central Processing Unit
i3
i2
i1
i2
i1
i1
store
Instruction Timing
i2
load
i1
3-41